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| CXD1961AQ DVB-S Frontend IC (QPSK demodulation + FEC) Preliminary For the availability of this product, please contact the sales office. Description The CXD1961AQ is a single chip DVB compliant Satellite Broadcasting Frontend IC, including dual A/D converter for analog baseband I/Q input, QPSK demodulator, Viterbi decoder Reed-Solomon decoder and Energy Dispersal descrambler. It is suitable for use in a DVB Integrated Receiver Decoder. 100 pin QFP (Plastic) Features * Dual 6 bit A/D converter Absolute Maximum Rating (Ta = 25C, GND = 0V) * QPSK demodulator * Power Supply VDD -0.5 to +4.6 V Multi-symbol rate operation * Input Voltage VIN -0.5 to VDD + 0.5 V Nyquist Roll off filter ( = 0.35) * Output Voltage VOUT -0.5 to VDD + 0.5 V Clock recovery circuit * I/O Voltage VI/O -0.5 to VDD + 0.5 V Carrier recovery circuit * CPU I/F pin Vcpuif -0.5 to +5.5 V AGC control (PWM output) * Storage Temperature Tstg -55 to +150 C * Viterbi decoder Constraint length 7 Recommended Operating Condition Truncation length 144 (Ta = 0 to 75C, GND = 0V) BER monitor of QPSK demodulator output * Power Supply VDD 3.15 to 3.45 V * Frame synchronization circuit * Input High level VIH 0.7 x VDD to VDD + 0.5 V * Convolutional de-interleaver * Input Low level VIL 0.3 to 0.2 x VDD V * Reed-Solomon decoder (204,188) BER monitor of Viterbi decoder output * Energy dispersal descrambler * CPU interface circuit I2C bus interface (5V input capability) * Package QFP 100pin * Operating frequency 20 to 30MSPS * Power consumption 750mW (@3.3V 30MSPS typical) * Process 0.4m CMOS Technology Application DVB-S Set Top Box (Satellite) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- PE97854-PS CXD1961AQ OPOUT VCOEN OPOUT OPXIN AVS1 AVS2 AVS4 AVD4 FSYNC VCOC AVD1 QSYNC Block Diagram AVD0 RT0 RB1 QIN IIN RT1 AVD2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 AVS0 RB0 1 2 analog I/O 2ch ADC Sampling Clock VCO PLL 80 VDD9 79 CR7 78 CR6 77 CR5 QPSK Demodulator 76 CR4 75 VSS8 74 VDD8 73 CR3 72 CR2 71 CR1 NCO Viterbi Decoder 70 CR0 69 CKV 68 AGCPWM 67 VSS7 66 VDD7 65 VCK De-interleaver 64 VDT VDD0 3 VSS0 TEST1 4 5 TEST2 6 TEST3 7 TEST4 8 NC 9 VDD1 10 VSS1 11 SDAT/SCL 12 SCLK 13 SEN/SDA 14 VDD2 15 VSS2 16 TCK 17 TMS 18 TEST6 19 TEST7 20 CK8OUT 21 RESET 22 TE 23 VDD3 24 VSS3 25 PKTCLK 26 BYTCLK 27 PKTERR 28 DATA0 29 DATA1 30 Oscillator VSS9 63 XI 62 XO 61 AVS3 60 AVD3 59 SDA 58 SCL 57 TEST22 56 TEST21 55 TEST20 54 VSS6 53 VDD6 52 TEST19 51 TEST18 Reed-Solomon Decoder CPU I/F I2C bus Energy Dispersal decoded data & clock 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DATA4 TEST8 VSS5 TEST12 TEST11 TEST10 Typical Block Diagram LNB Amp SAW I/Q detector LPF SONY CXD1961AQ LPF VCO PLL 479.5MHz 90 Reference OSC LPF Crystal Clock QPSK + FEC Data Micro Controller -2- TEST13 TEST14 TEST15 TEST16 TEST17 DATA3 DATA2 DATA5 DATA6 DATA7 TEST9 VDD4 VDD5 VSS4 CXD1961AQ Functional Description (1) A/D Converters The CXD1961AQ has dual 6 bit A/D converters to quantize the analog baseband I/Q signal. The sampling rate is two times the symbol rate. The input range is determined by the external resisters. See reference circuit (1). The DC offset cancellation function is set by setting CPU I/F register 1E,1F(hex). (2) Clock Recovery Circuit The CXD1961AQ can operate at multiple symbol rates between 20 to 30MSPS. Initial sampling clock frequency is set by a 24 bit control word via CPU I/F register 18, 19, 1A (hex). This control word is written to the numerically controlled oscillator (NCO). The internal clock recovery loop feeds clock error data to the above NCO to provide sampling timing correction. The relation between the symbol rate and the control word is; (symbol rate) = 4 x NCO [23:0] x Fcrystal / 224 (Hz) where NCO [23:0] is the 24 bit control word and Fcrystal is crystal frequency (Hz). The clock recovery loop coefficient and the loop gain are set by setting CPU I/Fregister 0C (hex) accordingly. See reference circuit (2). The recovered symbol clock can be monitored at Pin 69. There are three internal sub-registers to save the NCO control word. By setting the number of the preset subregister, the control word corresponded to the certain symbol rate is set to the internal NCO. Contents of the sub-register are deleted by power off or reset by pin 22. Refer to the explanation of CPU I/F register 0D (hex). (3) Carrier Recovery Circuit Any carrier frequency offset which remains on the analog baseband I/Q input is compensated by the internal digital costas loop. The capture range is Rs/8 (Rs: symbol rate). When the carrier capture is performed, QPSK lock flag QSYNC goes high. QSYNC is output at Pin 82 and CPU I/F register 09 (hex). In QPSK synchronization, the carrier offset estimation value is output at CPU I/F register 02 (hex) as AFC [7:0]. The frequency offset is; (carrier offset) = Rs x AFC [7:0] / 512 (Hz) where AFC7 is the sign bit that represents the direction of the offset. (4) Nyquist Roll off Filter The Nyquist roll off filter for each channel are embedded. The roll off factor is 0.35. -3- CXD1961AQ (5) Auto Gain Control By comparing the demodulated I/Q amplitude (I2 + Q2) and the reference level which is set via CPU I/F register 21 (hex), the AGC control signal is generated as PWM output at Pin 68. The polarity of the AGC can be reversed by setting CPU I/F register 10 (hex). For the Tuner interface, see the reference circuit (4). (6) Viterbi Decoder The punctured decoding and Viterbi decoding are performed on the demodulated I and Q data. The punctured rate is programmable from 1/2 to 7/8. When punctured mapping is performed, Viterbi lock flag at CPU I/F register 09 (hex) goes one. Bit error count at QPSK demodulator output is estimated and output to CPU I/F register 03, 04 (hex) as 16 bit data. (7) Frame synchronization and Deinterleaver By detecting the MPEG2 sync word 47 (hex), the synchronization of the data packet is achieved, and the convolutional deinterleaver then recovers the original data order. (8) Reed-Solomon Decoder In DVB systems, 16 parity bytes are added to the 188 data bytes, so that up to 8 error bytes are correctable by the Reed-Solomon decoder. If there are more than 8 error bytes in a packet, error correction is not performed and the packet error flag PKTERR (Pin 28) goes high during the packet to indicate that the packet is not correctable. The MSB of the second byte of the uncorrectable packet also becomes one. Bit error count at Viterbi decoder output is estimated and output every 1280 packet (=204 x 8 x 1280 bit) to CPU I/F register 06, 07 (hex) at a resolution of 16 bits. (9) Energy Dispersal Descrambler Energy dispersal descrambling is represented by the polynomial X15 + X14 + 1. The initial sequence is loaded when an inverted MPEG sync word B8 (hex) is detected. When MPEG sync word including inverted one is detected every 204 bytes, the lock flag of the whole IC "FSYNC" goes high. FSYNC is output at Pin 83 and CPU I/F register 09 (hex). -4- CXD1961AQ (10) CPU Interface The CXD1961AQ has an I2C bus interface. Serial clock SCL is Pin 58 and serial data in out SDA is Pin 59. Slave address is "1101 111" (DChex). 0 *** STA: start condition STP: stop condition ACK: acknowledge XACK: no acknowledge 0 Slave address 1101 111 1 Output data for sub-address N (hex) *** Both SCL and SDA have 5V input capability. -5- XACK ACK ACK ACK STA CXD1961AQ Pin Configuration OPOUT VCOEN OPOUT OPXIN AVS1 AVD2 AVS2 AVS4 AVD4 FSYNC AVD1 VCOC QSYNC AVD0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 AVS0 RB0 VDD0 VSS0 TEST1 TEST2 TEST3 TEST4 NC 1 2 3 4 5 6 7 8 9 80 VDD9 79 CR7 78 CR6 77 CR5 76 CR4 75 VSS8 74 VDD8 73 CR3 72 CR2 71 CR1 70 CR0 69 CKV 68 AGCPWM 67 VSS7 66 VDD7 65 VCK 64 VDT 63 XI 62 XO 61 AVS3 60 AVD3 59 SDA 58 SCL 57 TEST22 56 TEST21 55 TEST20 54 VSS6 53 VDD6 52 TEST19 51 TEST18 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDD1 10 VSS1 11 SDAT/SCL 12 SCLK 13 SEN/SDA 14 VDD2 15 VSS2 16 TCK 17 TMS 18 TEST6 19 TEST7 20 CK8OUT 21 RESET 22 TE 23 VDD3 24 VSS3 25 PKTCLK 26 BYTCLK 27 PKTERR 28 DATA0 29 DATA1 30 RT1 DATA3 DATA7 VDD5 TEST12 TEST11 TEST10 TEST13 TEST14 TEST15 TEST16 DATA2 DATA5 DATA6 VSS4 TEST9 VDD4 DATA4 TEST8 VSS5 -6- TEST17 VSS9 RT0 RB1 QIN IIN CXD1961AQ Pin List No. 1 2 3 4 5 to 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 to 33 34 35 36 to 38 39 to 43 44 45 46 to 48 49 to 52 Symbol AVS0 RB0 VDD0 VSS0 TEST1 to 4 NC VDD1 VSS1 SDAT/SCL SCLK SEN/SDA VDD2 VSS2 TCK TMS TEST6 TEST7 CK8OUT RESET TE VDD3 VSS3 PKTCLK BYTCLK PKTERR DATA0 to 4 VDD4 VSS4 DATA5 to 7 TEST8 to 12 VDD5 VSS5 TEST13 to 15 TEST16 to 19 Analog VSS Ref. voltage input Digital VDD Digital VSS CMOS input No Connection Digital VDD Digital VSS 3-state CMOS output 3-state CMOS output In out with Pull up Digital VDD Digital VSS Input with pull up Input with pull up CMOS input Input with pull up CMOS output Input with pull up Input with pull down Digital VDD Digital VSS 3-state CMOS output 3-state CMOS output 3-state CMOS output 3-state CMOS output Digital VDD Digital VSS 3-state CMOS output CMOS in out Digital VDD Digital VSS CMOS in out CMOS input I/O type -7- CXD1961AQ No. 53 54 55 to 57 58 59 60 61 62 63 64 65 66 67 68 69 70 to 73 74 75 76 to 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 Symbol VDD6 VSS6 TEST20 to 22 SCL SDA AVD3 AVS3 XO XI VDT VCK VDD7 VSS7 AGCPWM CKV CR0 to 3 VDD8 VSS8 CR4 to 7 VDD9 VSS9 QSYNC FSYNC AVD4 AVS4 CPOUT AVD2 VCOC OPXIN OPOUT AVS2 VCOEN RT1 AVD1 Digital VDD Digital VSS CMOS input 5V input 5V open drain in out Crystal VDD Crystal VSS Oscillator output Oscillator input CMOS in out CMOS in out Digital VDD Digital VSS CMOS output CMOS in out CMOS output Digital VDD Digital VSS CMOS output Digital VDD Digital VSS CMOS output CMOS output Analog VDD Analog VSS 3-state CMOS output Analog VDD Analog input Analog input Analog output Analog VSS CMOS input Ref. voltage input Analog VDD I/O type -8- CXD1961AQ No. 95 96 97 98 99 100 Symbol QIN AVS1 RB1 RT0 AVD0 IIN Analog input Analog VSS Ref. voltage input Ref. voltage input Analog VDD Analog input I/O type Note) Apply 0.1F capacitor to every power supply terminal and reference voltage input (RB0, RB1, RT0, RT1). -9- CXD1961AQ Pin Explanation 1. A/D Converter Function Analog signal input Top reference level input Bottom reference level input Analog power supply (+3.3V) Analog ground See reference circuit (1) ADC for I input Pin No. 100 98 2 99 1 Pin name IIN RT0 RB0 AVD0 AVS0 ADC for Q input Pin No. 95 93 97 94 96 Pin name QIN RT1 RB1 AVD1 AVS1 2. Clock Recovery 2-1. Crystal Function Crystal oscillator (output) Crystal oscillator (input) Crystal oscillator power supply (+3.3V) Crystal oscillator ground See reference circuit (3) Pin No. 62 63 60 61 Pin name XO XI AVD3 AVS3 2-2. VCO * OP-Amp Function Charge Pump output Charge pump power supply (+3.3V) Charge pump ground VCO control voltage input VCO enable (H: enable) OP-Amp negative input OP-Amp output VCO * OP-Amp power supply (+3.3V) VCO * OP-Amp ground See reference circuit (2) Pin No. 86 84 85 88 92 89 90 87 91 Pin name CPOUT AVD4 AVS4 VCOC VCOEN OPXIN OPOUT AVD2 AVS2 - 10 - CXD1961AQ 2-3. Clock Recovery Function Clock error output (for clock recovery by VCXO) Recovered symbol clock output (switchable to sampling clock output) Pin No. 70 to 73 76 to 79 69 Pin name CR0 to 3 CR4 to 7 CKV 3. Carrier Recovery Function Carrier lock flag (H: lock) Pin No. 82 Pin name QSYNC 4. AGC Function AGC control data (PWM output) See reference circuit (4) Pin No. 68 Pin name AGCPWM 5. Viterbi Decoder Function Viterbi clock output Viterbi decoded data output Pin No. 65 64 Pin name VCK VDT These pins can be fixed to ground by setting CPU I/F register 0E (hex). 6. Frame Synchronization Function Frame synchronization flag (H: sync) Pin No. 83 Pin name FSYNC - 11 - CXD1961AQ 7. Reed-Solomon Decoder/Data output Function Data output clock (parallel mode) Byte clock (Serial mode) Viterbi clock Packet clock (H: data, L: parity) Uncorrectable packet flag Data output (Parallel mode) LSB data (Serial mode) serial data (MSB first) Data output (Parallel mode) DATA7 = MSB (Serial mode) Hi-Z Pin No. 27 26 28 29 Pin name BYTCLK PKTCLK PKTERR DATA0 30 to 33 DATA1 to 4 36 to 38 DATA5 to 7 Output mode (Serial or Parallel) is switched by setting CPU I/F register 0F (hex). 8. CPU Interface Function I2C bus serial clock input I2C bus serial data in out Pin No. 58 59 Pin name SCL SDA 9. Reset Function Reset (L: reset/fix H for normal use) Pin No. 22 Pin name RESET 10. Power Supply Function Digital power supply (+3.3V) Pin No. Pin name 10, 15, 24, 34, 44, 53, VDD0 to 9 66, 74, 80 11, 16, 25, 35, 45, 54, VSS0 to 9 67, 75, 81 Digital ground Apply 0.1F capacitor to every power supply terminal. - 12 - CXD1961AQ 11. Test / Others Function Test mode enable (Fix L for normal use) Test clock (Fix H for normal use) Test mode Control (Fix H for normal use) Test input (Fix L) Test output (connect nothing) Test in out (Fix L) Tuner interface (3 wire mode) Serial data output (I2C bus mode) Serial clock output Tuner interface (3 wire) Clock output Tuner interface (3 wire mode) Latch enable output (I2C bus mode) Serial data in out Clock output (crystal frequency/8) No Connection Pin No. 23 17 18 Pin name TE TCK TMS 5 to 8, 20 TEST1 to 4, TEST7 49 to 52 TEST16 to 19 55 to 57 TEST20 to 22 19 39 to 43 46 to 48 12 13 14 21 9 TEST6 TEST8 to 12 TEST13 to 15 SDAT/SCL SCLK SEN/SDA CK8OUT NC - 13 - CXD1961AQ Electrical Characteristics Description Symbol rate Crystal Frequency DATA0 to 7 - BYTCLK falling edge (Parallel output mode PBYCK = 0) PKTCLK - BYTCLK falling edge (Parallel output mode PBYCK = 0) PKTERR - BYTCLK falling edge (Parallel output mode PBYCK = 0) DATA0 to 7 - BYTCLK rising edge (Parallel output mode PBYCK = 1) PKTCLK - BYTCLK rising edge (Parallel output mode PBYCK = 1) PKTERR - BYTCLK rising edge (Parallel output mode PBYCK = 1) Serial output mode cycle time (Serial output mode) DATA0 to 7 - BYTCLK hold time (Serial output mode) PKTCLK, PKTERR - BYTCLK setup time (Serial output mode) PKTCLK, PKTERR - BYTCLK hold time (Serial output mode) I2C bus Serial clock cycle time I2C bus Data setup time I2C bus Data hold time Symbol Rs Fxtal tDB0 tPB0 tEB0 tDB1 tPB1 tEB1 tSOC tDBH tPBS tEBH FscI tDSI tDHI 100 0 75 75 75 75 75 75 16 12 6 10 Min. 20 (Ta = 0 to 75C, VDD = 3.3V) Typ. Max. 30 32 Unit MSPS MHz ns ns ns ns ns ns ns ns ns ns 400 kHz ns ns Timing Waveform (1) Parallel output mode, PBYTCK = 0 tPB0 tEB0 tPB0 tEB0 PKTCLK PKTERR BYTCLK DATA [0:7] tDB0 tDB0 - 14 - CXD1961AQ (2) Parallel output mode, PBYTCK = 1 tPB1 tEB1 tPB1 tEB1 PKTCLK PKTERR BYTCLK DATA [0:7] tDB1 tDB1 (3) Serial output mode (Example of R = 3/4) tPBS tEBH tEBH PKTCLK tSOC PKTERR BYTCLK DATA0 tDBH (4) I2C Bus interface 0.6s tDSI SDA SCL 1.3s 1.3s tDHI 0.6s 0.6s - 15 - CXD1961AQ CPU Interface Registers Sub address (hex) 00 01 02 03 READ REGISTER 04 05 06 07 08 09A 09B 0A 0B 0C 0D 0E 0F 10 11 12 13 WRITE REGISTER 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 Name INP_LEV PWM_VAL AFC_VAL MSB bit7 INP7 PWM7 AFC7 bit6 INP6 PWM6 AFC6 QBEC6 bit5 INP5 PWM5 AFC5 bit4 INP4 PWM4 AFC4 bit3 INP3 PWM3 AFC3 QBEC3 bit2 INP2 PWM2 AFC2 QBEC2 bit1 INP1 PWM1 AFC1 QBEC1 LSB bit0 INP0 PWM0 AFC0 QBEC0 QBEC8 VBEC0 VBEC8 VBER0 OFQ0 ID CM0 CM8 OFC0 CE0 SRS0 QBEC_LO QBEC7 W QBEC5 QBEC4 QBEC15 QBEC14 QBEC13 QBEC12 QBEC11 QBEC10 QBEC9 VBEC6 VBEC5 VBEC4 VBEC3 VBEC2 VBEC1 QBEC_UP VBEC7 R VBEC_LO W VBEC15 VBEC14 VBEC13 VBEC12 VBEC11 VBEC10 VBEC9 -- OFI3 RO2 OFI2 NAK CM6 CM14 OFC6 MQS2 RATE2 DOH1Z RO1 OFI1 -- CM5 CM13 OFC5 MQS1 RATE1 DOPS RO0 OFI0 FSYNC CM4 CM12 OFC4 MQS0 QBER1 OFQ3 QBER0 OFQ2 VBER1 OFQ1 -- CM1 CM9 OFC1 CE1 SRS1 VBEC_UPR VCOLK CODE/BER DC_OFST FLAG CM_LOW CM_UPR CM7 CM15 OFC7 MQS3 -- VSYNC QSYNC CM3 CM11 OFC3 AK1 CM2 CM10 OFC2 AK0 -- RATE0 SRSAVE PPKER CAR_OFST PBYCK MQS/CLK CODE/SRS OUT_CNT MOD_CNT AGC/RST QTH VTH SINV MAGC QTH5 VTH4 TUD17 TUD27 TUD37 PPKCK MBYCK VCKVDT SEL09 SYSSEL DFSKIP RSSKIP TUNSEL TUNEN MFSYNC AGCLP PAGC QTH4 VTH3 TUD16 TUD26 TUD36 TUD46 TUD56 NCO6 NCO14 NCO22 MVSYNC CKVSEL QPRST QTH3 VTH2 TUD15 TUD25 TUD35 TUD45 TUD55 NCO5 NCO13 NCO21 QTH2 VTH1 TUD14 TUD24 TUD34 TUD44 TUD54 NCO4 NCO12 NCO20 -- -- BSI0 TCAR1 QTH1 VTH0 TUD13 TUD23 TUD33 TUD43 TUD53 NCO3 NCO11 NCO19 VTRST QTH0 TVS2 TUD12 TUD22 TUD32 TUD42 TUD52 NCO2 NCO10 NCO18 RSRST VCORST TQBEC1 TQBEC0 TVS1 TUD11 TUD21 TUD31 TUD41 TUD51 NCO1 NCO9 NCO17 TVS0 TUD10 TUD20 TUD30 TUD40 TUD50 NCO0 NCO8 NCO16 -- -- BSQ0 TUN_DAT1 TUD47 TUN_DAT2 TUD57 TUN_DAT3 NCO7 TUN_DAT4 NCO15 TUN_DAT5 NCO23 SYM_RATE1 CALRST CADRST CLKRST SYM_RATE2 SYM_RATE3 -- BSI3 -- BSI2 GAIN1 TQS0 BSC6 REF6 -- BSI1 GAIN0 RANGE FSYSEL FSYTHD -- BSQ3 TCAR0 -- BSQ2 -- BSQ1 CAR_RST RSTEN N.A. DC_BIAS CAR/DC TQS1 BSC7 REF7 MOFST OFSTEN OFSTGN FLOOP TRACK FLMOD FLSTEP QTLEV1 QTLEV0 BSC5 REF5 BSC4 REF4 BSC3 REF3 BSC2 REF2 BSC1 REF1 BSC0 REF0 Input "0" to write registers which are not assigned ("--"). - 16 - CXD1961AQ Description of CPU Interface Registers Sub address 00 (hex) INP7 to INP0 (MSB) (LSB) Read INP_LEV Input level estimation Upper 8 bit of I2 + Q2 of analog I/Q input. (Ex.) The value is about 40 (hex) when the analog I/Q amplitude is half the input range. Sub address 01 (hex) PWM7 to PWM0 (MSB) (LSB) Sub address 02 (hex) AFC7 to AFC0 (MSB) (LSB) AFC7: Sign Read PWM_VAL AGC PWM output value PWM output value of AGC control. Read AFC_VAL Carrier offset value Carrier offset estimation Carrier offset = (Symbol rate) x AFC [7:0] / 512 (Hz) Ex.) 20MSPS AFC [7:0] = 11110000 (bin) offset = 20MHz x (-16) / 512 = -625kHz In this case, by changing tuner PLL value by -625kHz, the offset may be cancelled. Read Read QBEC_LOW QBEC_UPR Bit error count at QPSK output Bit error count at QPSK output Sub address 03 (hex) Sub address 04 (hex) QBEC15 to QBEC0 (MSB) (LSB) Bit error count at the QPSK output (16 bit). Measuring period is set by TQBEC [1:0] of CPU I/F register 11 (hex) . BER is the ratio of QBEC [15:0] and the measuring period. QBEC [15:0] is valid when QSYNC, VSYNC and FSYNC are all High. Sub address 05 (hex) Sub address 06 (hex) VBEC15 to VBEC0 (MSB) (LSB) Read Read VBEC_LOW VBEC_UPR Bit error count at Viterbi output Bit error count at Viterbi output Bit error count at the Viterbi output (16 bit). Measuring period is 204 x 8 x 1280 = 2,088,960. BER is the ratio of VBEC [15:0] and 2,088,960. VBEC [15:0] is valid when QSYNC, VSYNC and FSYNC are all High. - 17 - CXD1961AQ Sub address 07 (hex) RO2 to RO0 Read CODE/BER Code rate and BER Current punctured rate (code rate) RO2 0 0 0 1 1 1 1 RO1 0 1 1 0 0 1 1 RO0 1 0 1 0 1 0 1 Code rate 1/2 2/3 3/4 4/5 5/6 6/7 7/8 QBER1 to QBER0 4 level BER indicator of QPSK output. This indicator is valid when QSYNC, VSYNC and FSYNC are all High and TQBEC [1:0] = 10 (bin). TQBEC [1:0] is in register 11 (hex). QBER1 0 0 1 1 QBER0 0 1 0 1 Bit Error Rate more than 10-2 10-3 < <10-2 10-4 < <10-3 less than 10-4 VBER1 to VBER0 4 level BER indicator of Viterbi output. This indicator is valid when QSYNC, VSYNC and FSYNC are all High. VBER1 0 0 1 1 VBER0 0 1 0 1 Bit Error Rate more than 10-2 10-3 < <10-2 10-4 < <10-3 less than 10-4 - 18 - CXD1961AQ Sub address 08 (hex) OFI3 to OFI0 OFI3: Sign OFQ3 to OFQ0 OFQ3: Sign Read DC_OFST DC offset level of A to D converter DC offset value of the I channel A/D converter. DC offset value of the Q channel A/D converter. In both cases, the value is depend on the operation mode. MOFST (reg. IE) 0 1 Operating mode Offset bias mode Offset cancel mode OFI [3:0] / OFQ [3:0] Current offset value. Compensation value for each A/D converter. Refer to the explanation of register 1E (hex). Sub address 09 (hex)-A Read FLAG Status Flag Register 09 (hex) has an irregular structure. Two register -A and -B are correspond to the sub-address 09 (hex). When SEL09 of the register 0E (hex) is 0, register 09 (hex)-A is selected, else register 09 (hex)-B is selected. VCOLK This bit become 0 in case of abnormal oscillation of embedded VCO. NAK (Tuner interface I2C bus mode) This bit becomes 1 in case of no acknowledge from the tuner PLL. This bit becomes 1 iwhen Frame synchronization is achieved. FSYNC VSYNC This bit becomes 1 when the punctured mapping synchronization is achieved. QSYNC This bit becomes 1 when carrier lock is achieved. ID This bit is always 1. Sub address 09 (hex)-B Sub address 0A (hex) Read Read CM_LOW CM_UPR Constellation Monitor Constellation Monitor These registers can be access when SEL09 of register 0E (hex) is 1. CM15 to CM0 (MSB) (LSB) Monitor value of the QPSK constellation. This value depends on the AGC reference (reg. 21 (hex)). Refer to Fig.1. - 19 - CXD1961AQ Sub address 0B (hex) OFC7 to OFC0 OFC7: Sign Read CAR_OFST Carrier Capture offset value Offset frequency at the point of carrier capture (Latest offset frequency is output to register 02 (hex)) (offset frequency) = (Symbol rate) x OFC [7:0] / 1024 (Hz) Ex.) 20MSPS OFC [6:0] = 11110000 (bin) (offset freq.) = 20MHz x (-16) / 1024 = -312.5kHz Write MQS/CLK Qsync mode/Clock recovery Sub address 0C (hex) MQS3 to MQS0 (MSB) (LSB) Threshold for carrier lock detection AK1 to AK0 Clock recovery loop filter coefficient 00: Max. 11: min. Clock recovery loop filter gain 00: Min. 11: Max. Clock recovery range is approximately 200ppm with CE (1:0) = 11. CE1 to CE0 Sub address 0D (hex) RATE2 to RATE0 Write CODE/SRS Code rate select/Symbol rate select Code rate setting RATE2 0 0 0 1 1 1 1 RATE1 0 1 1 0 0 1 1 RATE0 1 0 1 0 1 0 1 Code rate R 1/2 2/3 3/4 4/5 5/6 6/7 7/8 SRSAVE By saving several NCO control word to sub registers initially, symbol rate can be changed by setting the number of the sub register in which the desired control word is saved. There are three sub registers. - 20 - CXD1961AQ SRS1 to SRS0 (To set the symbol rate directly without the above function) Set SRSAVE = 0, SRS [1:0] = (1,1) and set control word to registers 18, 19, 1A (hex). (To save control word to sub registers) Set SRSAVE = 1 and set sub register No. ((0, 0) or (0, 1) or (1, 0)) to SRS [1:0]. Then set control word to registers 18, 19, 1A (hex). The control word is set to both the clock recovery circuit and the selected sub register. (To set the symbol rate with the above function) Set SRSAVE = 0, and set sub register No. of control word to be set. The control word saved in the sub register is set to the clock recovery circuit. Sub address 0E (hex) PBYCK Write OUT_CNT Output control and polarity 0: For falling edge 1: For rising edge BYTCLK polarity DOH1Z 1: Output Hi-Z mode (PKTCLK, BYTCLK, PKTERR, DATA [7:0]) DOPS 0: Parallel output mode 1: Serial output mode Refer to Electric characteristics PPKER PKTERR polarity 0: PKTERR: H at uncorrectable packet 1: PKTERR: L at uncorrectable packet PPKCK PKTCLK polarity 0: PKTCLK: H at data / L at parity 1: PKTCLK: L at data / H at parity MBYCK 1: BYTCLK mask mode In this mode BYTCLK is forced Low during parity data output VCKVDT 1: Viterbi decode data VDT (Pin 64) and clock VCK (Pin 65) output enable 0: VDT and VCK are fixed low. SEL09 Read register 09 (hex)-A, -B selection 0: 09 (hex)-A is selected 1: 09 (hex)-B is selected - 21 - CXD1961AQ Sub address 0F (hex) SINV Write MOD_CONT Mode Control I/Q exchange 1: normal operation SYSSEL Not assigned. Input 0. DFSK1P 1: Nyquist roll off filter bypass mode RSSK1P 1: Reed-Solomon decoder bypass mode TUNSEL Tuner interface mode 0: I2C bus mode 1: 3 wire mode TUNEN 1: Tuner interface enable TUNSEL Don't care 0 1 TUNEN 0 1 1 Pin 12 Hi-Z clock out data out Pin 13 Hi-Z Hi-Z clock out Pin 14 Hi-Z data in out Latch Enable mode -- I2C bus 3 wire Refer to reference circuit (5). MFSYNC Parameter for frame synchronization protection 0: normal operation mode 1: powerful protection mode AGCLP AGC loop filter gain 1: normal operation 0: large gain - 22 - CXD1961AQ Sub address 10 (hex) MAGC Write AGC/RST AGC and Reset AGC mode 0: normal mode 1: bus control mode In normal mode, PWM output is controlled so that I2 + Q2 (register 00hex) should become approximately equal to the reference level set in register 21 (hex). In bus control mode, data of the register 21 (hex) is directly converted to PWM output. PAGC 0: For tuner whose gain increases by higher AGC control voltage 1: For tuner whose gain increases by lower AGC control voltage Select mode according to tuner AGC type. AGC polarity MVSYNC Input 0 CKVSEL CKV (Pin 69) output mode 0: symbol clock output 1: sampling clock output QPRST 1: QPSK block reset (set 0 for normal operation) To reset QPSK block, set this bit to 1 and then set this bit to 0 again. VTRST 1: Viterbi block reset (set 0 for normal operation) Reset operation is same as QPRST. RSRST 1: Deinterleaver and Reed-solomon block reset (set 0 for normal operation) Reset operation is same as QPRST. VCORST 1: NCO block reset (set 0 for normal operation) Reset operation is same as QPRST. - 23 - CXD1961AQ Sub address 11 (hex) QTH5 to QTH0 (MSB) (LSB) Write QTH Qsync Threshold and QBEC period Threshold for carrier lock detection These parameters relate to QTLEV [1:0] in register 1F (hex) and AGC reference 21 (hex). Ex.) QTLEV [1:0] = 01 AGC ref = 32 (hex) QTH [5:0] = 101000 TQBEC1 to TQBEC0 Count period of QPSK bit error count TQBEC1 TQBEC0 0 0 1 1 0 1 0 1 Count period 28 216 219 223 Select TQBEC [1:0] = 10 to use QPSK BER indicator (register 07 (hex)) Sub address 12 (hex) VTH4 to VTH0 Write VTH Viterbi sync threshold and period Threshold for punctured mapping synchronization 11110: Min. 00000: Max. TVS2 to TVS0 Detection period for punctured mapping synchronization 110: Min 000: Max. code rate 1/2 2/3 3/4 4/5 5/6 6/7 7/8 VTH4 to VTH0, TVS2 to TVS0 8B (hex) BB (hex) CB (hex) D3 (hex) DB (hex) E3 (hex) E3 (hex) - 24 - CXD1961AQ Sub address 13 (hex) Sub address 14 (hex) Sub address 15 (hex) Sub address 16 (hex) Sub address 17 (hex) (I2C bus mode) Write Write Write Write Write TUN_DAT1 TUN_DAT2 TUN_DAT3 TUN_DAT4 TUN_DAT5 Tuner control data Tuner control data Tuner control data Tuner control data Tuner control data Set TUNSEL = 0 and TUNEN = 1 in the register 0F (hex). 13 (hex): Tuner PLL IC slave address + 0 (write mode) 14 to 17 (hex): Write data (tuning parameter) I2C bus starts write operation when data setting to register 17 (hex) is finished. In case of no acknowledge from tuner PLL IC, NAK in the register 09 (hex)-A is set to 1. Set TUNSEL = 1 and TUEN = 1 in the register 0F (hex). 28 bits data (register 13 to 15 (hex) and upper 4bit of the register 16 (hex)) are transmitted serially. To start operation, dummy data setting to the register 17 (hex) is needed. Refer to the reference circuit (5). (3 wire mode) Sub address 18 (hex) Sub address 19 (hex) Sub address 1A (hex) NCO23 to NCO0 (MSB) (LSB) Write Write Write SYM_RATE1 SYM_RATE2 SYM_RATE3 Control word for multi-rate oscillation Control word for multi-rate oscillation Control word for multi-rate oscillation The relation between symbol rate and the control word of the NCO is: NCO [23:0] = (symbol rate) x 222 / (crystal frequency) Ex.) Symbol rate 20MSPS crystal 32MHz NCO [23:0] = 20 x 106 x 222 / 32 x 10-6 = 2,621,440 = 221 + 219 NCO21 = NCO19 = 1, other = 0 - 25 - CXD1961AQ Sub address 1B (hex) CARRST Write CAR_RST Carrier loop reset 1: Carrier loop filter reset Reset operation is same as QPRST (register 10hex) CADRST 1: Carrier recovery frequency loop reset Reset operation is same as QPRST (register 10hex) CLKRST 1: Clock recovery loop reset Reset operation is same as QPRST (register 10hex) RANGE Carrier capture range 0: Carrier capture range = Rs/8 1: Carrier capture range = Rs/16 FSYSEL Frame synchronization detector mode 0: Hard decision 1: Soft decision FSYTHD Frame synchronization threshold 0: Low 1: High Sub address 1C (hex) Write Input 0 to all bits. N.A. Not Assigned Sub address 1D (hex) Write DC_BIAS A/D Converter DC_BIAS DC offset is added to the output of the A/D converter when MOFST in the register 1E (hex) is 0. BSI3 to BSI0 DC offset for I channel A/D converter. BSI3: sign Offset range is from -8 to +7. BSQ3 to BSQ0 DC offset for Q channel A/D converter. BSI3: sign Offset range is from -8 to +7. - 26 - CXD1961AQ Sub address 1E (hex) RSTEN Write CAR/DC Carrier recovery and DC offset 1:Carrier loop filter reset enable (Set to 1 for normal operation) GAIN1 to GAIN0 Gain setting for carrier recovery loop GAIN1 0 0 1 1 GAIN0 0 1 0 1 Gain x1 x2 x4 x8 (default x1) TCAR1 to TCAR0 Mode setting for carrier recovery frequency loop: default TCAR [1:0] = 10. MOFST 1: A/D converter DC offset cancellation mode 0: A/D converter DC offset addition mode OFSTEN 1: A/D converter DC offset control (cancel or add) enable 0: A/D converter DC offset control (cancel or add) disable OFSTGN A/D converter DC offset cancellation loop filter gain 1: x1 0: x1/2 - 27 - CXD1961AQ Sub address 1F (hex) TQS1 to TQS0 Write CAR_MODE Carrier recovery mode Carrier lock detection period 00: min. 11: max. Default is TQS [1:0] = 10 FLOOP 0: Carrier recovery by phase loop 1: Carrier recovery by phase and frequency loop (default) TRACK default: 0 FLMOD 1: Carrier offset frequency is set by BSC [6:0]. 0: Carrier offset frequency is set by the internal loop. (default) FLSTEP default: 1 QTLEV1 to QTLEV0 Gain for carrier lock detection circuit. Default is QTLEV [1:0] = 00 Sub address 20 (hex) BSC7 to BSC0 BSC7: sign Write CAR_BIAS Carrier frequency offset bias Carrier offset frequency setting This mode is good when FLMOD = 1. (Carrier offset) = (Symbol rate) x BSC [7:0] / 1024 (Hz) Sub address 21 (hex) AGCR7 to AGCR0 Write AGC_REF AGC reference Input level reference for AGC operation Refer to the explanation of register 10 (hex) - 28 - CXD1961AQ Application Circuit (1) A/D Converter 390 Analog VSS 1k 0.1F 0.1F Connect AVD0 and AVD1 to analog +3.3V supply Baseband Q input Baseband I input 0.1F 0.1F 1k 0.1F 390 99 98 97 0.1F 1k 96 95 94 390 93 0.1F 100 AVD0 AVS1 1k 1 390 Analog VSS 0.1F 2 RB0 AVS0 CXD1961AQ (2) Clock Recovery circuit Connect AVD2 and AVD4 to analog +3.3V supply 15k Analog VSS 2.2F 0.1F 1k 92 91 90 89 88 100k 22 4.7F 10k 0.1F Analog VSS 86 85 84 87 OPOUT AVD2 VCOC AVS2 VCOEN CXD1961AQ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 29 - CPOUT OPXIN AVD4 AVS4 AVD1 RB1 RT0 RT1 IIN QIN CXD1961AQ (3) Crystal Crystal XI 63 470k XO 62 7pF AVS3 61 Digital VSS 7pF Crystal Daishinku AT-49 32.0MHz Connect AVD3 to ditital +3.3V supply AVD3 60 CXD1961AQ 0.1F (4) AGC This is an example of how to set AGC control voltage from 0 to 5V. Power supply for the OP-Amp is 7V. 20k AGCPWM 68 OP-Amp To tuner AGC input 5.6k 0.1F 10k CXD1961AQ Analog VSS (5) Tuner Interface (3 wire type) suitable for GEC Plessey SP5658 100 ENABLE 100 DATA 100 CLOCK 14 SEN/SDA SP5658 CXD1961AQ 13 SCLK 12 SDAT/SCL Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 30 - CXD1961AQ (5) Tuner Interface (I2C bus type) suitable to GEC Plessey SP5659 etc. (4 bytes of data can be written) +3.3V 10k 100 SDA 100 SCL 13 SCLK 12 SDAT/SCL 10k 14 SEN/SDA SP5659 CXD1961AQ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 31 - CXD1961AQ Appendix Fig.1 Constellation monitor output vs. C/N 104 Constellation monitor output 103 4 6 8 10 12 14 16 C/N [dB] 18 20 22 24 26 28 This figure is an example when AGCREF is set to 32 (hex). The monitor output value is proportional to AGCREF. Monitor output : CM [15:0] CPU I/F register 09-B (hex) and 0A (hex) - 32 - CXD1961AQ Package Outline Unit: mm 100PIN QFP (PLASTIC) 23.9 0.4 + 0.4 20.0 - 0.1 80 51 + 0.1 0.15 - 0.05 81 50 + 0.4 14.0 - 0.1 17.9 0.4 15.8 0.4 A 100 31 1 0.65 + 0.15 0.3 - 0.1 30 0.24 M + 0.35 2.75 - 0.15 + 0.2 0.1 - 0.05 0.15 DETAIL A 0.8 0.2 0 to 15 (16.3) PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.7g - 33 - |
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